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INTEGRATED CIRCUITS
DATA SHEET
UAA3500HL Pager receiver
Preliminary specification Supersedes data of 1999 Mar 30 File under Integrated Circuits, IC17 2000 Jan 18
Philips Semiconductors
Preliminary specification
Pager receiver
FEATURES * Double frequency conversion, zero-IF receiver with: - Configurable in all paging bands (130 to 930 MHz) - Low noise amplifier featured with four step Automatic Gain Control (AGC) - Down-conversion mixers - On-chip, zero-IF channel filter - I/Q, non-demodulated outputs - Highpass filters to remove DC offsets. * External Voltage Controlled Oscillator (VCO): - Both Local Oscillators (LOs) derived from the VCO. APPLICATIONS * FLEXTM, ERMES and POCSAG pagers * Remote control terminals. GENERAL DESCRIPTION The UAA3500HL is a one-chip pager receiver complying with POCSAG, FLEXTM and ERMES standards. The IC performs in accordance with specifications in the -10 to +55 C temperature range. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UAA3500HL LQFP48 DESCRIPTION
UAA3500HL
The UAA3500HL contains a front-end receiver, which can be configured through external components for any frequency band between 130 and 930 MHz. The back-end receiver consists of the channel filter and limiters. An external VCO ensures the Local Oscillator (LO) for the front-end. Designed in an advanced BiCMOS process, it combines high performance with low-power consumption and a high degree of integration, thus reducing external component costs and total radio size. Its first advantage is to remove the expensive SAW filter necessary in a superhet architecture, replacing it by an integrated, elliptic channel filter that provides 70 dB adjacent channel rejection. The receive front-end section consists of a low-noise amplifier that drives mixers through an external LC image rejection filter. The output drives the I and Q second mixers, whose outputs are at zero frequency. The receiver back-end section consists of filters (channel filtering), limiters (limited output required) and high-pass filters (DC block) to remove DC offsets. Outputs are I and Q, undemodulated signals. Its second advantage is to provide the two LO signals from one VCO only, tuned by a PLL. An on-chip frequency divider-by-2 and buffers provide the LO sources. Its third advantage is to provide two voltage regulators, allowing to obtain 1.0 and 1.8 V regulated voltages.
VERSION SOT313-2
plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
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Philips Semiconductors
Preliminary specification
Pager receiver
QUICK REFERENCE DATA SYMBOL VCC1 VCC2 ICC1(RX) PARAMETER supply voltage 1 (B++;see note 2) supply voltage 2 (B+; see note 2) supply current from B++ RX section on; DC tested fRF = 160 MHz fRF = 280 MHz fRF = 930 MHz ICC2(RX) supply current from B+ RX section on; DC tested fRF = 160 MHz fRF = 280 MHz fRF = 930 MHz NFRX receiver noise figure from RF input to 2nd mixer input fRF = 160 MHz fRF = 280 MHz fRF = 930 MHz Pi(ref) RF input sensitivity 3% BER fRF = 160 MHz; 1600 bits/s 2-level FSK fRF = 280 MHz; 1600 bits/s 2-level FSK fRF = 930 MHz; 6400 bits/s 2-level FSK fRF = 930 MHz; 6400 bits/s 4-level FSK ACR Tamb Notes adjacent channel rejection ambient temperature - - - - 65 -10 - - - - - 1.85 - - 2.35 CONDITIONS(1) MIN. 1.85 1.05
UAA3500HL
TYP. 2.1 1.4
MAX. UNIT 3.3 1.5 V V
2.4 2.4 2.7 1.3 1.4 2.3 2.7 3.1 4.4 -128.5 -128 -126.5 -123 70 +25
- - 3 - - 2.45 - - - - - - - - +55
mA mA mA mA mA mA dB dB dB dBm dBm dBm dBm dB C
1. For 930 MHz band; for other conditions see Chapters "DC characteristics" and "AC characteristics". 2. For B+ and B++, see Fig.3.
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37 40 35 36 38 39 42 41 46 47 16 17 18 25 24 28 23 43 44 VOLTAGE REGULATOR BIAS BUFFER 2 1 PMA LIMITER LIMITER OUTPUT 6 26 LNA OUTI AGCADJ RSSI AGCTAU OUTQ RSET LNAGND2 33 32 31 30 29 BUFFER LOIN 21 BUFFER 0 2 90
BLOCK DIAGRAM
Philips Semiconductors
VCC(DC) FILOUTA IMOUTA CAPI1A VCC(LO) CAPI1B IMINB IMOUTB FILOUTB VCC(FE) DRV2 M2GND FASTON FILINA IMINA FILINB DRV1 RXON M1GND
handbook, full pagewidth
Pager receiver
CAPI2A CAPI2B 3 4 45 5 GYROUTI VCC(O) CAPI3A CAPI3B
x x x
4
RFINA RFINB LNAGND1
GYRATOR REGULATOR
AGC
RSSI
34 27 7 OUTPUT 11 12
LIMITER PMA
LIMITER
CAPQ3A CAPQ3B OGND GYROUTQ
FCA022
UAA3500HL
BUFFER
8 15
BUFFER 22 LOGND 14 13 20 19 10 CAPQ2A CAPQ2B 9 48 BEGND
CAPQ1A GYRCO1 CAPQ1B GYRCO2
Preliminary specification
UAA3500HL
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Pager receiver
PINNING SYMBOL CAPI3B CAPI3A CAPI2A CAPI2B VCC(O) OUTI OUTQ OGND CAPQ2B CAPQ2A CAPQ3A CAPQ3B GYRCO2 GYRCO1 GYROUTQ DRV1 VCC(FE) VCC(DC) CAPQ1B CAPQ1A LOIN LOGND FASTON VCC(LO) DRV2 AGCADJ AGCTAU RXON LNAGND1 RFINB RFINA LNAGND2 RSET RSSI IMINA IMINB M1GND IMOUTA IMOUTB M2GND 2000 Jan 18 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DESCRIPTION 3rd DC filter (I path) external capacitor B (I path) 3rd DC filter (I path) external capacitor A (I path) 2nd DC filter (I path) external capacitor A (I path) 2nd DC filter (I path) external capacitor A (I path) output stage supply voltage B++ (I path) output I and Q signals (I path) output I and Q signals (Q path) output stage ground 2nd DC filter external capacitor B (Q path) 2nd DC filter external capacitor A (Q path) 3rd DC filter external capacitor A (Q path) 3rd DC filter external capacitor B (Q path) external resistor to set-up gyrator filter cut-off frequency external resistor to set-up gyrator filter cut-off frequency Q-gyrator output regulator driver (1.8 V) regulated voltage for front-end (1.8 V) input voltage from DC-to-DC converter (2.1 V) 1st DC filter external capacitor (Q path) 1st DC filter external capacitor (Q path) LO input LO strip ground fast mode enable regulated voltage for LO strip (1.0 V) regulator driver (1.0) AGC loop gain control AGC loop time constant receiver mode enable receiver LNA (Low Noise Amplifier) ground 1 LNA input B LNA input A receiver LNA ground 2 LNA current setup received signal strength indicator image rejection filter input A image rejection filter input B first mixer ground image rejection filter output A image rejection filter output B second mixers ground 5
UAA3500HL
Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
SYMBOL FILINB FILINA CAPI1A CAPI1B GYROUTI FILOUTA FILOUTB BEGND
PIN 41 42 43 44 45 46 47 48 band filter input B band filter input A
DESCRIPTION
1st DC filter external capacitor (I path) 1st DC filter external capacitor (I path) I-gyrator output band filter output to second mixers band filter output to second mixers receiver back-end ground
45 GYROUTI
47 FILOUTB
46 FILOUTA
39 IMOUTB
38 IMOUTA
40 M2GND
42 FILINA
CAPI3B CAPI3A CAPI2A CAPI2B VCC(O) OUTI OUTQ OGND CAPQ2B
1 2 3 4 5 6
41 FILINB
handbook, full pagewidth
37 M1GND
44 CAPI1B
43 CAPI1A
48 BEGND
36 IMINB 35 IMINA 34 RSSI 33 RSET 32 LNAGND2 31 RFINA
UAA3500HL
7 8 9 30 RFINB 29 LNAGND1 28 RXON 27 AGCTAU 26 AGCADJ 25 DRV2
CAPQ2A 10 CAPQ3A 11 CAPQ3B 12
GYRCO2 13
GYRCO1 14
GYROUTQ 15
DRV1 16
VCC(FE) 17
VCC(DC) 18
CAPQ1B 19
CAPQ1A 20
LOIN 21
LOGND 22
FASTON 23
VCC(LO) 24
FCA023
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Pager receiver
FUNCTIONAL DESCRIPTION Receiver front-end section The receiver front-end consists of an LNA, followed by the first and the second mixers. For operation at low frequency (160 and 280 MHz, for instance), the first mixer can be bypassed, saving some current. The image rejection is done by an external LC filter placed between the LNA, the first mixer and the antenna selectivity. The IF band is filtered by an external filter placed between the first mixer and the second mixers for the I and Q paths. The RF signals are in phase, and the LO signals are shifted by 90. The output signals are at zero frequency. To increase the immunity to interferers, an AGC loop controls the LNA gain by attenuating the RF input signal. Four steps of attenuation are possible (each having 8 dB), ranging therefore from 0 to 32 dB. The AGC loop threshold level and time constant may be controlled externally at pins AGCADJ and AGCTAU. The second LO I/Q phase shift is made by a quadrature divider, whose input is the VCO oscillating signal. The LNA current is setup by an external resistor. All the receivers (front-end and back-end) are turned on by pin RXON. Receiver back-end section The down-converted signal is amplified and then filtered by a Sallen-Key filter, which shows a notch at 15 kHz and about 6 dB rejection out-of-band. Then comes the first high-pass filter (DC block), followed by the gyrator filter, which performs an elliptic, 7-pole low-pass filtering. The signal is then amplified by the first limiter, filtered by the second DC block, amplified again, and filtered again by the third DC block. Finally, an output stage delivers the signal with rail-to-rail logic levels. Table 1 Switching signals on the receiver SECTION receive section powered-on receive section powered-off FASTON fast mode powered-on fast mode powered-off
UAA3500HL
The first, second and third DC block frequencies are set at 4, 8 and 12 Hz respectively by external 330 nF capacitors. The two voltage regulators are also activated by RXON. At the output of the gyrator filter, the signal is buffered and logarithmically converted. It then controls the AGC loop. To rapidly reach the DC operating point, a fast mode is built into the three DC blocks. LO The external VCO is AC-coupled at input LOIN. It is then buffered to drive the first mixer. LOIN also enters a quadrature divider-by-2, whose output signals are also buffered to drive the second mixers. The VCO frequency should be 23 of the input RF signal. The LO signal must be generated with an external frequency synthesizer and VCO or with a crystal oscillator. OPERATING MODES To use the IC, all VCC pins must be connected to the supply voltage B++ (2.1 V). The 1.8 V regulated voltage sinks current from B++ and the 1.0 V regulated voltage from B+ (1.4 V). In a typical application, the B+ supply is the battery and the B++ supply is the DC/DC converter located in the baseband chip. In normal operating mode, the receiver should be powered-on in fast mode. The fast mode can be turned off after several milliseconds. Table 1 gives the definition of the polarity of the switching signals on the receive section.
SIGNAL RXON
LEVEL HIGH LOW HIGH LOW
ON/OFF on off on off
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Philips Semiconductors
Preliminary specification
Pager receiver
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC GND Pl(max) Tj(max) P(max) Tstg Note 1. Pins short circuited internally must be short circuited externally. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) HANDLING All pins withstand the ESD test in accordance with "MIL-STD-883C class 2 (method 3015.5)". PARAMETER thermal resistance from junction to ambient CONDITIONS in free air supply voltage difference in ground supply voltage applied between all grounds maximum power input maximum operating junction temperature maximum power dissipation storage temperature note 1 PARAMETER CONDITIONS MIN. - - - - in stagnant air at 25 C - -65
UAA3500HL
MAX. 6 0.3 20 150 500 +150
UNIT V V dBm C mW C
VALUE 90
UNIT K/W
DC CHARACTERISTICS VCC = 2.1 V; Tamb = 25 C; 930 MHz band application, 3% BER and 1600 bits/s 2 level; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Pins: VCC(O), DRV1, VCC(FE), VCC(DC), VCC(LO) and DRV2 VCC1 VCC2 ICC1(RX) supply voltage 1 (B++; see note 1) supply voltage 2 (B+; see note 1) supply current from B++ over full temperature range over full temperature range RX section on; DC tested fRF = 160 MHz fRF = 280 MHz fRF = 930 MHz ICC2(RX) supply current from B+ RX section on; DC tested fRF = 160 MHz fRF = 280 MHz fRF = 930 MHz ICC1(pd) ICC2(pd) standby current from B++ standby current from B+ Power-down mode; DC tested Power-down mode; DC tested - - 1.85 0 0 1.3 1.4 2.3 0.01 0.01 - - 2.45 1 0.5 mA mA mA A A - - 2.35 2.4 2.4 2.7 - - 3 mA mA mA 1.85 1.05 2.1 1.4 3.3 1.5 V V
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Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Pins: RXON, FASTON, OUTI and OUTQ VIH VIL IIH IIL VCAP VCAP VCAP VRF VIMOUT HIGH-level voltage LOW-level voltage HIGH-level static current LOW-level static current VCC - 0.4 V pin at 0.4 V VCC - 0.3 VCC -0.3 -1 -1 1.20 - - - 1.40 VCC + 0.3 +0.4 +1 +1 V V A A V
Pins: CAPI1A, CAPI1B, CAPQ1A and CAPQ1B DC level RX section on 1.60
Pins: CAPI2A, CAPI2B, CAPQ2A, CAPQ2B DC level RX section on 1.40 1.57 1.80 V
Pins: CAPI3A, CAPI3B, CAPQ3A, CAPQ3B DC level RX section on 1.30 - - 1.57 1.90 - - V
Pins: RFINA and RFINB DC level RX section on 0.92 V
Pins: IMOUTA and IMOUTB DC level RX section on 0.17 V
Pins: VCC(LO) VVcc(lo) DC level RX section on 0.95 1.00 1.05 V
Pins: VCC(FE) VVcc(fe) VFILOUT VRSSI DC level RX section on 1.75 - 1.80 1.85 - 0.30 - 1.70 V
Pins: FILOUTA and FILOUTB DC level RX section on 0.24 V
Pins: AGCTAU and RSSI DC level RX section on; FASTON is LOW - RX section on; FASTON is HIGH VAGCTAU DC level RX section on; FASTON is HIGH 0 V V V VCC - 0.3 VCC 1.50 1.60
Pins: GYROUTI and GYROUTQ VGYROUT VOH VOL Note 1. For B+ and B++, see Fig.3. DC level RX section on Io = -5 A Io = 5 A 1.37 - - 1.42 1.47 V
Output stage HIGH-level output voltage LOW-level output voltage VCC - 0.2 - 0.2 - V V
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Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
AC CHARACTERISTICS VCC = 2.1 V; Tamb = 25 C; 930 MHz band application, 3% BER and 1600 bits/s 2 level; on evaluation board according to Fig.3; system measurement done using PCD5009, PCD5010 baseband; unless otherwise specified. SYMBOL Receiver Pi(ref) RF input sensitivity 3% BER fRF = 160 MHz; 1600 bits/s 2-level FSK fRF = 280 MHz; 1600 bits/s 2-level FSK fRF = 930 MHz; 6400 bits/s 2-level FSK fRF = 930 MHz; 6400 bits/s 4-level FSK G(PCFE) front-end conversion power gain from RF input to 2nd mixer input fRF = 160 MHz fRF = 280 MHz fRF = 930 MHz NFRX receiver noise figure from RF input to 2nd mixer input fRF = 160 MHz fRF = 280 MHz fRF = 930 MHz IP1 IP2 IP3 IM3 CCR ACR bl GAGC AGCth ton IQ RLNA 1 dB input compression point 2nd order intercept point 3rd order intercept point 3rd order intermodulation co-channel rejection adjacent channel rejection blocking immunity front-end gain reduction by AGC step AGC threshold establishment time IQ channel unbalance LNA current set resistor 160 MHz 280 MHz 930 MHz Rgyr LO fVCO VCO frequency -
2 3fRF
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
- - - - - - - - - - - 45 - 55 - 65 75 7
-128.5 - -128 -123 20 12.8 12.7 2.7 3.1 4.4 -38 - -33 - 5 70 80 8 25 - - 56 47 27 47 - - - - - - - - - - - - - - - 9 30 30 2 - - - - -126.5 -
dBm dBm dBm dBm dB dB dB dB dB dB dBm dBm dBm dB dB dB dB dB dB ms dB k k k k
from RF input to 2nd mixer input from 2nd mixer input to gyrator output from RF input to 2nd mixer input; note 1 3 signal measurement threshold +3 dB channel spacing = 25 kHz; from RF input to gyrator output frequency offset >1 MHz
above sensitivity until sensitivity +3 dB is reached
20 - - - - - -
gyrator cut-off frequency set resistor
cut-off frequency = 8.5 kHz
-
MHz
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Philips Semiconductors
Preliminary specification
Pager receiver
UAA3500HL
SYMBOL LNA GLNA
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
RF amplifier power gain
from RF input to image filter output fRF = 160 MHz fRF = 280 MHz fRF = 930 MHz - - 12.5 - - - - -21 -0.5 - - 20 16.2 14.2 1.8 1.9 2.2 -27 -17.6 0 10.2 -22 - - - - - 2.5 - - - 13 - - - - - - dB dB dB dB dB dB dBm dBm
NFLNA
RF amplifier noise figure
from RF input to image filter output fRF = 160 MHz fRF = 280 MHz fRF = 930 MHz
IP1LNA IP3LNA First mixer GFM NFFM IP1FM IP3FM GvBE IP3BE fcut-off fcut-off Note
1 dB input compression point 3rd order intercept point
from RF input to image filter output from RF input to image filter output
1st mixer power gain 1st mixer noise figure 1 dB input compression point 3rd order intercept point
dB dB dBm dBm
-12.5 -11 from 2nd mixer input to gyrator output from 2nd mixer input to gyrator output 42 - - 150 45 -59 4 400
Second mixer, PMA, Sallen-Key, 1st DC block and gyrator filter voltage gain 3rd order intercept point dB dBm
1st DC block cut-off frequency cut-off frequency measured at gyrator output; FASTON is LOW measured at gyrator output; FASTON is HIGH Hz Hz
1. The two tones for intermodulation test would normally be set at 2 and 4 or 4 and 8 channels for type approval tests i.e 930 and 930.1 or 930.1 and 930.2 MHz.
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Philips Semiconductors
Preliminary specification
Pager receiver
APPLICATION INFORMATION
UAA3500HL
handbook, full pagewidth
BAND FILTER GYROUTI 330 nF IMAGE FILTER
GYROUTI
FILOUTB
FILOUTA
IMOUTB
IMOUTA
38
M2GND
48 CAP13B 330 nF 1
47
46
45
44
43
42
41
40
39
M1GND
37 36 35 34
CAPI1B
CAPI1A
BEGND
FILINA
FILINB
IMINB IMINA RSSI RSSI RLNA
CAP13A 2 CAP12A 3
330 nF
B++ OUTI OUTQ
CAP12B 4 VCC(O) 5 OUTI 6 OUTQ 7 OGND 8 CAPQ2B 9
33 RSET
32 LNAGND2 31 RFINA RFIN 30 RFINB
UAA3500HL
29 LNAGND1 28 27 26 25 14 15 16 17 18 19 20 21 22 23 24 RXON AGCTAU AGCADJ DRV2 B+ 100 k RXON 10 nF
330 nF
CAPQ2A 10 CAPQ3A 11
330 nF
CAPQ3B 12 13
GYRCO2
GYRCO1
GYROUTQ
CAPQ1B
CAPQ1A
VCC(DC)
FASTON
DRV1
VCC(FE)
LOIN
LOGND
47 k GYROUTQ 10 nF 100 k
B++ 100 pF 10 F
330 nF VCO
FASTON 100 pF 10 F
B++
FCA024
Electrical diagram of the UAA3500HL demonstration board for FLEXTM applications. All matching is to 50 for measurement purposes. B+ = 1.4 V; B++ = 2.1 V.
Fig.3 Demonstration board diagram.
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VCC(LO)
15 k
Philips Semiconductors
Preliminary specification
Pager receiver
PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
UAA3500HL
SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC JEDEC MS-026 EIAJ EUROPEAN PROJECTION A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
ISSUE DATE 97-08-01 99-12-27
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Philips Semiconductors
Preliminary specification
Pager receiver
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
UAA3500HL
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Pager receiver
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable suitable(2) recommended(3)(4) recommended(5) suitable not not suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not
UAA3500HL
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
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15
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465008/02/pp16
Date of release: 2000
Jan 18
Document order number:
9397 750 06478

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